1. Field
The present disclosure herein relates to a delay locked loop and, more specifically, to a delay locked loop including a duty correction circuit and a duty correction method thereof.
2. Description of the Related Art
Typically, a synchronous semiconductor memory device capable of being mounted on a data processing device such as a computer or a portable electronic device adopts a delayed locked loop (hereinafter referred to as “DLL”).
A DLL generates an internal clock signal phase-locked with an external clock signal as an output clock signal to perform an operation of a semiconductor device synchronously with the external clock signal. That is, because timing delay unavoidably occurs when an internally used clock signal passes a block buffer and a transmission line of a semiconductor device, the DLL serves as a phase adjuster to synchronize the internal clock signal with the external clock signal.
In case of a semiconductor memory device using an output clock signal generated from a DLL, a signal timing margin may be maximally secured when a duty cycle rate of the output clock signal is maintained at 50 percent. However, the duty ratio of the output clock signal frequently deviates from the 50 percent due to characteristics of a jitter outside the DLL and non-uniform delay values of delay elements inside the DLL. Thus, a duty correction circuit has been conventionally adopted in a DLL to perform a duty correction operation.
Especially, in case of an intellectual property (IP) that is sensitive to a duty of a clock, like a double data rate (DDR) type semiconductor memory device, it is almost essential that a duty correction circuit (hereinafter referred to as “DCC”) be embedded in a DLL.
Significant issues of the DCC are a more accurate duty correction operation, easy implementation of the DCC, and a smaller area occupied by a chip.
However, a conventional duty correction circuit has generated an output clock signal of a 50-percent duty ratio by using a 180-degree phase delayed clock signal and a 0-degree phase delayed clock signal. Such a duty correction circuit needs to additionally include a half cycle time delay line (HCDL) and a matching delay line (MDL) in a DLL. That is, the HCDL is needed to measure a one-clock period and generate a 180-degree clock signal delayed as great as a half cycle and the MDL is needed to compensate intrinsic delay of the HCDL.
After obtaining the number (N) of delay cells required for one cycle, the HCDL uses N/2 delay cells to practically delay a half cycle. Thus, when N is an odd number, a quantization error is inevitably reflected on a duty by one-half unit delay.
With the recent trend toward high-speed operation, high integration density, and low power consumption of semiconductor devices, there is a need for a duty correction circuit which is capable of securing a duty ratio of more improved accuracy and a delay locked loop (DLL) adopting the duty correction circuit.